• Synopsys expanded collaboration with TSMC to deliver silicon-proven IP and certified, AI-powered EDA flows for advanced process nodes including N3 and N2 families, A16 with Super Power Rail, and A14.
• Partnership targets faster development of next-generation AI and high-performance computing chips through improved power, performance, and area results.
• Synopsys reported successful silicon bring-up of low-power M-PHY v6.0 IP on TSMC N2P, supporting earlier deployment of high-speed interface IP for AI systems.
• Work on TSMC 3DFabric packaging expands enablement for CoWoS at 5.5x reticle interposer sizes, supporting larger multi-die designs.
• Joint development includes agentic run assistance in Synopsys Fusion Compiler for TSMC A14 using NanoFlex Pro architecture to raise design productivity.

Disclaimer: This news brief was created by Public Technologies (PUBT) using generative artificial intelligence. While PUBT strives to provide accurate and timely information, this AI-generated content is for informational purposes only and should not be interpreted as financial, investment, or legal advice. Synopsys Inc. published the original content used to generate this news brief via PR Newswire (Ref. ID: 202604221500PR_NEWS_USPR_____SF41025) on April 22, 2026, and is solely responsible for the information contained therein.